Cadence Announces Samsung Electronics Co., Ltd. Sign-Off Endorsement of BuildGates and PKS Static Timing Analysis in ASIC Design Flows
SAN JOSE, Calif.--(BUSINESS WIRE)--April 29, 2002--Cadence Design
Systems, Inc. (NYSE:CDN - news) today announced that Samsung Electronics Co.,
Ltd. (SEC) has issued a sign-off endorsement for the static timing
analysis (STA) technology embedded within BuildGates® synthesis and
Cadence® Physically Knowledgeable Synthesis (PKS) software for
application specific integrated circuit (ASIC) design flows. SEC now
includes BuildGates synthesis and PKS libraries for 0.13-micron and
0.18-micron technologies in its STD150 and STD130 design kits.
The STA engine is integrated within the Cadence SP&R
(synthesis/place-and-route) product line. This gives customers a
unique sign-off quality timing environment from RTL to GDSII.
"We have been performing static functional and timing verification
for our multi-million gate ASIC designs in order to deliver fast
design cycle times for our customers. We offer our customers a robust
static timing sign-off methodology that has been proven in our deep
sub-micron (DSM) production ASIC designs," said Jeong-Taek Kong,
Ph.D., vice president of CAE Team, Semiconductor R&D Center at SEC.
"We are pleased to endorse the fast, accurate STA in BuildGates and
PKS for 0.13-micron and 0.18-micron technology flows for our
customers."
By embedding the STA capability directly into the SP&R
front-to-back design flow, Cadence delivers excellent timing
correlation between synthesis and place-and-route, reducing
verification and design closure time. This fast and incremental timing
engine enables designers to quickly identify and fix timing problems
without leaving the SP&R design environment, eliminating the need for
a separate STA tool in the design flow.
"Samsung's endorsement is an important milestone for Cadence and
reaffirms our technology leadership in SP&R," said Kook-Jin Lim,
president of Cadence Korea. "The high capacity and high performance of
BuildGates and PKS with the integrated, sign-off STA delivers rapid
timing closure in the Samsung ASIC flow. We are committed to
supporting Samsung and our mutual customers with our state-of-the-art
technology to address their future design needs, and look forward to
an enduring collaborative relationship."
About Samsung
Samsung Electronics Co., Ltd. is a global leader in semiconductor,
telecommunication, and digital convergence technology. Samsung
Electronics employs approximately 64,000 people in 89 offices in 47
countries. Samsung Electronics is the world's largest producer of
memory products, Smart Card Chips, Display Driver ICs, TFT-LCDs, CDMA
mobile phones, monitors and VCRs. Samsung Electronics consists of four
main business units: Digital Media Network, Device Solution Network,
Telecommunication Network and Digital Appliance Network Businesses.
For more information, please visit the web site,
http://www.samsungelectronics.com.
About Cadence
Cadence is the largest supplier of electronic design technologies,
methodology services, and design services. Cadence solutions are used
to accelerate and manage the design of semiconductors, computer
systems, networking and telecommunications equipment, consumer
electronics, and a variety of other electronics-based products. With
approximately 5,600 employees and 2001 revenues of approximately $1.4
billion, Cadence has sales offices, design centers, and research
facilities around the world. The company is headquartered in San Jose,
Calif., and traded on the New York Stock Exchange under the symbol
CDN. More information about the company, its products and services are
available at www.cadence.com.
Cadence, BuildGates, and the Cadence logo are registered
trademarks of Cadence Design Systems, Inc. All other trademarks are
the property of their respective owners.
Contact:
Cadence Design Systems, Inc.
Parvesh Bal-Sandhu, 408/894-2512
parvesh@cadence.com
or
Cadence Korea, Ltd.
Danny Chung, 82-31-728-3007
danny@cadence.com
